As semiconductor designs move from traditional monolithic ICs toward 2.5D and 3D IC architectures, physical verification must extend beyond individual dies to the entire multi-die assembly. Chiplets, interposers, packages and die-to-die interfaces introduce new alignment and connectivity challenges that cannot be fully addressed by conventional die-level verification alone.
Calibre 3DSTACK from Siemens EDA extends Calibre signoff verification into advanced packaging and 3D IC design. It enables engineers to perform assembly-level DRC, LVS and connectivity verification across multi-die systems while continuing to work with established design flows and packaging data formats.
What is Calibre 3DSTACK?
Calibre 3DSTACK is a physical verification solution designed for heterogeneous multi-die systems, including 2.5D IC, 3D IC and advanced semiconductor packaging. It extends the Calibre verification environment from individual dies to the complete package assembly.
This allows engineers to verify whether dies, interposers and package components are correctly aligned and connected, while performing signoff checks across the entire system. The solution supports workflows that combine different dies, technologies and process nodes within the same package.
Why is multi-die physical verification important?
A die may successfully pass its own DRC and LVS checks but still encounter issues after being integrated into a multi-die package. Misaligned bumps, incorrect die placement, broken connections or interposer connectivity errors can affect the manufacturability and reliability of the final system.
For this reason, advanced packaging requires verification at the assembly level, where the relationships between dies, interposers and package structures can be checked as a complete system.
Calibre 3DSTACK key features
1. Multi-die system-level DRC and LVS verification
Calibre 3DSTACK extends Calibre die-level signoff verification to complete 2.5D and 3D stacked-die systems. Designers can perform DRC and LVS verification across multiple dies and package structures while using familiar Calibre verification flows.
2. Die, package and interposer alignment checks
Accurate alignment is critical in multi-die packaging. Calibre 3DSTACK allows designers to verify the relative placement and alignment of dies, interposers and package interfaces before physical assembly.
3. System-level connectivity verification
Calibre 3DSTACK supports connectivity checking across the complete multi-die package assembly. Engineers can verify whether dies, interposers, bumps and package connections match the intended system-level connectivity.
4. Interposer and package connectivity checking
The solution can also verify standalone interposer and package connectivity without requiring the complete individual die design databases. This gives packaging teams additional flexibility when working with heterogeneous components or third-party dies.
Calibre 3DSTACK for 2.5D and 3D IC design
In advanced IC packaging, multiple dies or chiplets may be integrated through silicon interposers, redistribution layers or other package structures. These architectures improve system integration but also create verification challenges that cross traditional IC and package boundaries.
Calibre 3DSTACK provides a unified verification environment that allows engineering teams to check the complete assembly rather than reviewing each component independently. This is particularly important for heterogeneous integration where dies from different processes or technology nodes are combined within one system.
Benefits of using Calibre 3DSTACK
- Extend Calibre signoff verification from individual dies to complete multi-die assemblies.
- Detect alignment and connectivity issues before manufacturing.
- Support verification of heterogeneous 2.5D and 3D IC designs.
- Reuse familiar Calibre verification flows and design data formats.
- Reduce the risk of costly package rework caused by late-stage verification errors.
Frequently asked questions about Calibre 3DSTACK
What is Calibre 3DSTACK used for?
Calibre 3DSTACK is used for physical and connectivity verification of multi-die assemblies, including 2.5D IC, 3D IC, chiplet, interposer and advanced packaging designs.
Can Calibre 3DSTACK perform DRC and LVS?
Yes. Calibre 3DSTACK extends Calibre DRC and LVS verification to the assembly level, enabling verification across multiple dies and package structures.
Is Calibre 3DSTACK suitable for 3D IC and chiplet designs?
Yes. The solution is designed to support heterogeneous multi-die systems and advanced packaging architectures such as 2.5D and 3D IC designs.
Learn more
- 3D-IC design using Calibre 3DSTACK
- Top 5 Calibre IC design solutions in IC verification
- 3D IC and the system-technology co-optimization (STCO) approach
Source: Siemens EDA
Contact Vietbay for more information about Calibre 3DSTACK and Siemens EDA solutions.
