3D-IC technology is gaining attention as an alternative to complement Moore’s Law, which is approaching its physical limits. Unlike traditional 2D IC design, 3D-IC…
Screenshot of the Calibre Interactive GUI showing multiple running jobs. The Calibre Multiple Job Submission (MJS) interface optimizes the IC design verification process As…
Business challenges Integration and verifcation of highly complex AI architecture Create next-generation ultra-performance AI NPU chiplets ETRI's AI NPU Development History The Electronics and…
The Calibre Auto-Waivers tool provides fast, accurate, automated recognition, removal, and tracking of waived design rule violations during DRC. It eliminates costly time and…
As semiconductor designs move from traditional monolithic ICs toward 2.5D and 3D IC architectures, physical verification must extend beyond individual dies to the entire…
Comprehensive industry-leading technology for Calibre multi-patterning decomposition, verification, and error debugging. Supports all major foundry methodologies and processes, and provides unique tool integrations and…
At Calibre Pattern Matching, SoC designers must balance customization of SRAM for better performance against potential impacts on yield. Enhancing SRAM debugging with pattern…
The Calibre nmDRC Recon technology reduces iteration and debug time by minimizing the rules and data required for DRC in early design iterations. Results…