In operational theory, optimizing a bottleneck or critical path within a process can have a significant impact on overall efficiency. This principle is particularly relevant to the integrated circuit (IC) design and verification process, where the time spent on debugging can directly affect verification schedules and time to market.
1. Debugging – A Bottleneck in IC Design Verification
In chip design and verification, debugging has become one of the most time-consuming stages. According to a study referenced in Siemens EDA materials, debugging can account for approximately 47% of total verification time for a typical application-specific integrated circuit (ASIC) design.
The challenge becomes even greater when designs span multiple levels of abstraction, with analog and digital blocks interleaved within hierarchical structures. This makes it more difficult to trace connectivity and identify the root cause of errors when relying solely on traditional debugging methods.
Debugging tools primarily rely on waveform analysis, test reports, and log files. When engineers have to continuously switch between multiple sources of information, additional time may be required to establish relationships between signals, design structures, and the underlying causes of errors.
As a result, a visual debugging environment that provides deep observability and supports multiple modeling approaches, boundary-element configurations, and standard verification methodologies is becoming increasingly important for modern AMS verification workflows.
2. AMS Mixed-Signal Visualizer – A Visual Approach to AMS Verification
To address these challenges, Symphony Pro, a component of the Solido Simulation Suite, integrates Mixed-Signal Visualizer (MS Visualizer), a visual debugging environment specifically designed for modern AMS verification. MS Visualizer focuses on giving engineers a more intuitive view of the design while bringing the information required for debugging together within a unified workflow.
2.1. Visualize the Design with Multiple Windows
MS Visualizer provides IC verification engineers with an overall view of the design through dedicated windows for hierarchy, netlist, source code, and variables. These views are dynamically updated as users navigate through the design.
This clear visualization is particularly useful when working with complex “sandwich” structures, where analog and digital blocks are interleaved within the design hierarchy—a common characteristic of modern IC designs.
MS Visualizer provides dedicated windows for monitoring different aspects of the design, including:
- Hierarchy
- Netlist
- Source code
- Variables
These windows update dynamically as users navigate through the design. This allows engineers to trace relationships between components without continuously switching between separate tools or information sources.
2.2. Automatically Generate Schematics
Automatically generated schematics help engineers visualize design connectivity, check port mapping, and quickly identify inconsistencies in large hierarchical designs. This visual schematic generation reduces the need for manual searching and helps engineers quickly narrow down potential issues during debugging.
2.3. Analyze Mixed-Signal Nets
MS Visualizer can display both the analog and digital representations of a signal simultaneously, allowing engineers to observe the relationship between the two domains within the same debugging workflow.
This capability supports verification of signal-domain conversions, including:
- A2D (Analog-to-Digital)
- D2A (Digital-to-Analog)
2.4. Troubleshoot Design Issues
MS Visualizer supports troubleshooting through deep observability and a visual debugging workflow. Instead of relying entirely on waveform analysis, test reports, or log files, engineers can also access information about design structure, connectivity, and signal behavior.
To learn more about how Mixed-Signal Visualizer can simplify and improve AMS verification, Siemens EDA provides an in-depth White Paper. The document provides detailed information about the MS Visualizer environment, along with case studies demonstrating the solution’s effectiveness on real customer designs.
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