The best way to create a System on a Chip is with design IP: blocks that perform common functions such as interfaces to standard buses such as AMBA® AXI or PCIe. How do you then check that your chip works with the IP? You need to create stimulus that follows the protocol, but who has time to become an expert? The best way to verify your design is with Verification IP, or VIP.
Siemens Questa Verification IP (QVIP) is available for a wide range of protocols such as AXI, AHB, PCIe/NVMe, Ethernet, USB, Serial, plus DRAM and Flash memories. QVIP works with both SystemVerilog and VHDL designs, and easily integrates into a UVM testbench.
Questa Verification IP Integration Flow
Here are the four steps to connect Questa Verification IP to your testbench. The best part is that you can do the first three with the QVIP tool, Configurator, which also generates the files for the final step.
Steps 1
Configurator reads your top netlist and creates a schematic symbol. You connect it to QVIP blocks such as an AXI master, plus clock and reset. The QVIP code, including the bus functional model and SystemVerilog Assertions are inside a single module, which reduces the number of connections.
Steps 2
How wide are your RTL buses? How should the QVIP work with protocol features such as the RLAST signal in AXI? Specify these details in Configurator, either starting with a preexisting configuration or your own custom values.
Steps 3
Questa Verification IP comes with a library of randomizable sequences for many protocols to get you started quickly, plus a generic read/write API to create stimulus specific to your design.
Steps 4
Configurator generates a complete UVM testbench and netlist plus scripts, and support files for all major simulators. You can debug either interactively or after simulation completes. Questa Verification IP generates multiple log files so you can quickly see the high level transactions, and also the low level protocol-specific signals.
(Source: Siemens)
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