As IC and SoC designs become larger and more complex, physical verification is becoming one of the more time-consuming stages of chip development. Particularly at advanced process nodes, a single Design Rule Check (DRC) run can generate millions or even billions of violations that need to be analyzed.
The challenge goes beyond detecting violations. It also raises several questions: Where should engineers start debugging? Which violations are related? And which underlying systematic causes should be addressed first?
Calibre Vision AI was developed by Siemens EDA to address this challenge by combining high-speed DRC data processing, full-chip visualization, and analysis based on Artificial Intelligence/Machine Learning.
According to Siemens, the solution helps design teams quickly identify critical issues, recognize patterns and potential causes, shorten DRC debugging cycles, and support improvements in design quality.
The Challenges of DRC Debugging in Large IC Designs
With traditional methods, engineers often need to examine large numbers of individual violations. This approach becomes difficult to scale when a design contains multiple blocks, hierarchy levels, and millions of DRC results.
As violation counts increase, loading data, classifying violations, and identifying root causes can take significantly longer. This is particularly evident in large SoC designs, where multiple blocks are developed and verified in parallel.
Calibre Vision AI shifts the approach from “examining individual violations” to “identifying groups of systematic issues.”
AI-powered Signals – Grouping Related Violations
One of the core technologies in Calibre Vision AI is Signals.
AI/ML algorithms automatically analyze DRC results and group violations with similar characteristics or causes into Signals. Instead of addressing thousands of individual violations, engineers can focus on a group that shares a common pattern and identify an underlying issue affecting multiple violations at once.
The system can automatically classify Signals into seven categories, helping engineers quickly recognize systematic issues and prioritize areas for debugging.
According to Siemens, a notable feature is that this clustering capability works without requiring users to build their own training datasets or configure specialized AI settings before use.
This also shows that Calibre Vision AI is more than a Generative AI chatbot. Here, AI is applied directly to an engineering problem: analyzing, classifying, and identifying relationships between DRC violations.
Full-chip Heatmap – Seeing the Overall Picture Before Exploring the Details
Alongside AI clustering, Calibre Vision AI provides an intelligent violation density heatmap to visualize violation density across the entire chip.
Rather than opening individual violations to locate problem areas, engineers can quickly identify hotspots with high concentrations of violations, recognize patterns across the design, and then drill down into specific blocks or violations.
According to Siemens’ fact sheet, the visualization engine can display millions of violations and synchronize views and analysis panels as users interact. Engineers can therefore switch between full-chip views and detailed analysis while maintaining the complete debugging context.
Siemens’ product page also states that Calibre Vision AI uses an efficient OASIS results format to support the processing of very large DRC databases and chip-level results analysis at scale.
Hierarchical Debugging and Improved Collaboration
In large SoC projects, DRC debugging is rarely the responsibility of a single engineer. Chip integration teams and block teams need to communicate continuously to determine where violations occur and who is responsible for resolving them.
Calibre Vision AI supports hierarchical debugging, allowing violations to be isolated by chip, block, or hierarchy. Teams responsible for individual blocks can focus on their own scope while retaining the context of the entire design.
Capabilities such as Bookmarks, shared analysis states, and ASCII export also make it easier to share debugging states and analysis results between teams.
The solution can also integrate with layout viewers and place-and-route tools, allowing engineers to view and address violations in familiar design environments without completely changing their existing workflows.
How Does Calibre Vision AI Bring AI into Physical Verification?
Calibre Vision AI is part of the Calibre nmPlatform ecosystem and is integrated with Calibre nmDRC and other Calibre tools.
An important point is that Calibre Vision AI does not replace the DRC engine or rule deck. Calibre nmDRC continues to check designs against the design rules.
Vision AI focuses on the next step: helping engineers interpret large volumes of DRC results, recognize patterns, identify systematic issues, and organize the debugging process more effectively.
Put simply:
Calibre nmDRC detects violations → Calibre Vision AI helps engineers understand and resolve them faster.
This highlights the value of applying AI to physical verification: accelerating computation while helping engineers focus on the right issues, reduce repetitive debugging tasks, and move designs closer to tapeout readiness.
Explore Calibre Vision AI
For teams developing large SoCs, working with advanced-node designs, or facing increasing numbers of DRC violations, Calibre Vision AI offers a new approach to chip-level DRC debugging: full-chip visualization, AI-powered clustering, hierarchical analysis, and collaboration within a single workflow.
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